Digital circuits such as board level systems and integrated circuit (IC) devices, including field programmable gate arrays (FPGAs) and microprocessors, use clocking signals for a variety of reasons. For example, synchronous systems use global clock signals to synchronize various circuits across the board or IC device. However, as the complexity of digital circuits increases, clocking schemes for synchronous systems become more complicated. Many complex digital circuits such as microprocessors and FPGAs have multiple clock signals at different frequencies. For example, in some microprocessors, internal circuits are clocked by a first clock signal at a first frequency while input/output (I/O) circuits are clocked by a second clock signal at a second frequency. Typically, the second frequency is slower than the first frequency.
Multiple clock generating circuits can be used to generate the multiple clock signals; however, clock generating circuits typically consume a large amount of device or board space. Therefore, most systems use one clock generating circuit to generate a first clock signal and a specialized circuit to derive other clock signals from the first clock signal. For example, clock dividers are used to generate one or more clock signals of lower clock frequencies from an input clock signal.
FIG. 1A shows a conventional clock divider 100 that receives an input clock signal I.sub.-- CLK and generates a divided-by-two clock signal CLK.sub.-- D2, a divided-by-four clock signal CLK.sub.-- D4, and a divided-by-eight clock signal CLK.sub.-- D8. Clock divider 100 comprises a three-bit counter 110. Input clock signal I.sub.-- CLK is applied to the clock terminal of three-bit counter 110. Three-bit counter 110 drives clock signals CLK.sub.-- D2, CLK.sub.-- D4, and CLK.sub.-- D8 on output terminals O0, O1, and O2, respectively. Output terminal O0 is the least significant bit, output terminal O1 is the second least significant bit, and output terminal O2 is the most significant bit of three-bit counter 110.
FIG. 1B is a timing diagram for clock divider 100. As shown in FIG. 1B, input clock signal I.sub.-- CLK has a clock period P.sub.-- I. Clock period P.sub.-- 2 of divide-by-two clock signal CLK.sub.-- D2 is twice as long as clock period P.sub.-- I. Thus the frequency of clock signal CLK.sub.-- D2 is half the frequency of input clock signal I.sub.-- CLK. Similarly, clock periods P.sub.-- 4 and P.sub.-- 8 are four times and eight times as long as clock period P.sub.-- I, respectively. Thus, the frequencies of clock signals CLK.sub.-- D4 and CLK.sub.-- D8 are one-fourth and one-eighth the frequency of input clock signal I.sub.-- CLK, respectively.
In many digital systems, fixed clock divider circuits such as clock divider 100 do not provide enough flexibility. For example, an FPGA that operates internally with a clock rate of 100 MHz might be coupled to an external circuit that operates at a maximum rate of 33.3 MHz. Thus, a clock division circuit in the FPGA would need to divide the internal 100 MHz clock by three to operate with the external circuit. However, the same FPGA may be coupled to a second external circuit, which operates at a maximum rate of 50 MHz. For maximum performance of the second external circuit, the clock division circuit in the FPGA would need to divide the internal 100 MHz clock by two. Clock divider 100 is incapable both of dividing a clock frequency by three and of generating a variable output signal. Therefore, there is a need for a variable clock divider that generates an output clock signal having a desired frequency, where the desired frequency is a fraction of the frequency of an input clock signal.